SESD05A32D
Specifications
Specifications
Marking Code
57
Case
DFN1006
Circuit Figure
Fig.1
Peak Power Dissipation 8*20μsec PPPP(W)
450
Reverse Stand-Off Voltage VRWM(V)
5
Max Clamping Voltage VC (V) @ IPP
14
Off-State Capacitance 1MHz Zero dc Bias CO (PF)
200
Peak Pulse Current 8x20μsec IPP (A)
32
Reverse Leakage IR (μA) @ VRWM
1
