SESD05DFBW
Specifications
Specifications
Marking Code
5T
Case
DFN1006
Circuit Figure
Fig.4
Peak Power Dissipation 8*20μsec PPPP(W)
40
Reverse Stand-Off Voltage VRWM(V)
5
Max Clamping Voltage VC (V) @ IPP
13
Off-State Capacitance 1MHz Zero dc Bias CO (PF)
0.6
Peak Pulse Current 8x20μsec IPP (A)
3
Reverse Leakage IR (μA) @ VRWM
0.5
