SESD05LCD3
Specifications
Specifications
Marking Code
U3
Case
DFN1006-3L
Circuit Figure
Fig.5
Peak Power Dissipation 8*20μsec PPPP(W)
50
Reverse Stand-Off Voltage VRWM(V)
5
Max Clamping Voltage VC (V) @ IPP
12
Off-State Capacitance 1MHz Zero dc Bias CO (PF)
1
Peak Pulse Current 8x20μsec IPP (A)
4
Reverse Leakage IR (μA) @ VRWM
0.5
