SESD12DCFBW
Specifications
Specifications
Marking Code
DD
Case
DFN1006
Circuit Figure
Fig.2
Peak Power Dissipation 8*20μsec PPPP(W)
200
Reverse Stand-Off Voltage VRWM(V)
12
Max Clamping Voltage VC (V) @ IPP
27
Off-State Capacitance 1MHz Zero dc Bias CO (PF)
26
Peak Pulse Current 8x20μsec IPP (A)
7
Reverse Leakage IR (μA) @ VRWM
0.5
